RTLViz is ArchGen's open-source Python tool that generates interactive, high-fidelity block diagrams from Verilog code. It integrates with any IDE via MCP and has over 300 downloads. Install it with pip install rtlviz.

ChipOS is ArchGen's end-to-end agentic automation platform for semiconductor design. Its vision is to add intelligence to every stage of the Spec-to-GDSII development flow using specialized AI agents that collaborate across the semiconductor stack.

ArchGen | AI Agents for Semiconductor Design

The Architecture

Agentic Automation Core

We are building an end-to-end framework where specialized agents collaborate across the semiconductor stack.

Physical Design Agent

Automating the path to GDSII. We employ intelligent agents for macro placement, pin assignment, and floorplanning optimization to minimize congestion and resolve timing violations early in the flow.

RTL Visualization

Gain instant clarity into your design. Our semantic engine instantly generates interactive, high-fidelity block diagrams from Verilog, allowing effortless navigation through complex hierarchies.

Waveform Debugger

Slashing debug time by 10x. Our agents autonomously parse massive simulation logs and waveform datasets (VCD/FSDB) to pinpoint root causes of failures and suggest RTL fixes in real-time.

Our Progress

The ArchGen Stack

Establishing the foundation for the next generation of silicon design.

OPEN SOURCE

The semantic engine for hardware engineers. Used by thousands to visualize and inspect complex RTL hierarchies with AI-driven depth.

300+ DOWNLOADS ~300 users excluding bots (View Chart)

VIEW ON PYPI

CHIP-OS BETA

CHIP-OS SUITE

Our broader agentic framework is in early access. Partnering with industry leaders to deploy Architect, RTL, and Verification agents in production.

RESERVE EARLY ACCESS

Documentation

Get Started with RTLViz

Integrate ArchGen intelligence into your existing Verilog workflows in minutes.

Install

Install the RTLViz semantic engine via Python package manager.

SHELL

pip install rtlviz

Configure

Automatically configure your IDE for the semantic server.

SHELL

rtlviz setup

Ask Agent

After setup, ask your AI assistant on side panel:

PROMPT

"Use rtlviz MCP to generate a diagram for the in <path to code>"

FAQ

Frequently Asked Questions

Quick answers about our platform, tools, and what we're building.

What is ArchGen?

ArchGen is an AI-powered ecosystem for semiconductor design. It uses AI agents to automate the Spec-to-GDSII chip development flow, eliminating the manual grind of traditional EDA tools through agentic automation.

How does AI help chip design?

AI agents automate repetitive tasks in chip design such as RTL visualization, physical design floorplanning, timing closure, and waveform debugging. ArchGen's agents can reduce physical design time from months to weeks by autonomously optimizing placement, routing, and verification.

What tools does ArchGen offer?

ArchGen offers RTLViz, an open-source semantic engine for generating interactive RTL block diagrams from Verilog code (pip install rtlviz), and ChipOS Suite (in beta), a broader agentic framework with Architect, RTL, Physical Design, and Verification agents.

What is RTLViz?

RTLViz is an open-source Python tool with 300+ downloads that generates interactive, high-fidelity block diagrams from Verilog code. It works with any IDE via MCP integration. Install it with pip install rtlviz.

What is ChipOS?

ChipOS is ArchGen's end-to-end agentic automation platform. Its vision is to add AI intelligence to every stage of chip design, from specification to GDSII, using specialized agents that collaborate across the semiconductor stack.

Can't find what you're looking for? Reach out to us at hari@archgen.tech

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